1. Field of the Invention
The present disclosure relates generally to memory systems, and more specifically, to a bypass system and method that performs a bypass process that mimics clock to data memory read timing, including mimicking timing in the read domain of a multiport register file.
2. Description of the Related Art
A bypass system may be used for testing on-chip timing to determine whether data or information received from a memory has arrived at a destination within a target time frame. In a typical bypass operation, data are provided to the memory interface and provided back out to a destination without actually writing data into the memory array or reading data from the memory array. In a conventional bypass system, a simple interface, such as a set of flip-flops, buffers, latches, pass gates, or the like, conveys the input data received at the memory input port directly to the output port completely bypassing all memory functions including timing functions. The timing of the memory read process, however, has not been incorporated so that the results are not accurate.